This invention is concerned with a code error control system which is well suited for use in a teletext broadcast, where character and figure digital information is transmitted in a multiple mode during the vertical retrace blanking period of a TV signal. In particular, the invention is concerned with a code error correction decode circuit that can recover as many bit errors as possible which take place during transmission by means of error-correction.
An error correcting data transmission system of this kind using a TV channel is described in Japanese patent laid open publications Nos. 133751/84, 181841/84, and 216388/84, where data are first coded in packets, then transmitted and decoded with error correction facility. One packet consists of 272 bits, of which 190 bits are information bits and the remaining 82 bits are parity bits.
The circuit construction of a code error correction decode circuit used in the above system is shown in FIG. 1. In FIG. 1, 1 stands for a CPU bus line which is connected to a CPU (which is not shown in FIG. 1), the input terminal of output port 2, and the output terminal of input port 3. Output port 2 provides original data 5 to error correction circuit 4. Error correction circuit 4, which contains a parallel-serial converter, a serial-parallel converter, a syndrome register, and so on, corrects (272,190) code data. Error correction circuit 4 provides corrected data 6 and error status signal 7 to the said input port 3.
Now, operations which take place in the diagram of FIG. 1 will be described. First, original data are provided to output port 2 from CPU via CPU bus line 1. The original data received by output port 2 get corrected in error correction circuit 4 and are converted to corrected data 6. Corrected data 6 are provided to input port 3 and then sent to CPU via CPU bus line 1.
On the completion of error correction of one packet of data, error correction circuit 4 generates error status signal 7 that indicates the condition of the syndrome register, i.e., whether it is "0" or not, and sends it on CPU bus line 1 by way of input port 3. The "0" condition of the syndrome resistor means that either original data are error-free or they are corrected completely. Therefore, CPU gets information on validity of corrected data 6 on CPU bus line 1 by examining the error status signal.
The conventional technique explained above, however, has the following drawbacks.
In FIG. 1, suppose that signals are transferred between CPU and error correction circuit 4 in units of 8 bits=1 byte via CPU bus line 1. Then 34 byte-times are required for CPU to provide 1 packet (=272 bits) of original data to the error correction circuit, and the same amount of time is necessary for the error correction circuit to provide 1 packet of corrected data to CPU.
Moreover, in the Japan's teletext broadcast, it is possible to send up to 12 packets of data in one vertical period (=16.67 ms) and the total transfer time for 12 packs of data between CPU and the error correction amounts to as much as 816 byte-times (=34.times.2.times.12). These transfer operations are performed by write and read commands provided by CPU, and during the period for transfer operations CPU is so often required by them that it has not enough time for other jobs in the teletext broadcast such as decoding and generating display format. In particular, as the error correction process of error correction circuit 4 is performed asynchronously with the operation of CPU, CPU should detect every time when the error correction of one packet of original data gets completed, and upon detection of it, CPU issues a command necessary for the resulting corrected data provided by input port 3. Therefore, other jobs for which CPU is responsible during the same period of time are so often interrupted.
As explained above, in the conventional technique, one circuit of which is shown in FIG. 1, so much CPU time is required for the job of error correction that CPU cannot control all the other jobs necessary for the receiving and display required in the teletext broadcast.
In the second place, in the circuit shown in FIG. 1, it is only possible to know that data corrected in the correction circuit are completely correct or not, and information concerning the number of corrected bits is unavailable. It is necessary to judge the instant signal value to be "1" or "0" at each time point in order to convert received code data into their corresponding digital code, and for this purpose a correctly chosen threshold voltage is necessary. To obtain a correctly chosen threshold voltage, a feedback process is necessary between threshold voltage and the corresponding error which occured with it.
In the third place, though an invention of repeating a correction process with varying threshold values for a majority circuit used in it is described in said Japanese patent laid open publication No. 181841/84, the invention is no longer effective when original data contain too many error-bits. In this case, the repetition of a correction process means simply a waste of time.
Moreover, in the above case of too many error bits, the repetition of a correction process may result in an increase in error bits.